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features ? ic distinguishes the signal st rength of several transmitters via rssi (received signal strength indicator) output minimal external circuitry requirements, no rf components on the pc board except matching to the receiver antenna high sensitivity, especi ally at low data rates sensitivity reduction possib le even while receiving fully integrated vco low power consumption due to configurable self-polling with a programmable time frame check supply voltage 4.5v to 5.5v operating temperature range ?40c to +105c single-ended rf input for easy adaptation to / 4 antenna or printed antenna on pcb low-cost solution due to high integration level esd protection according to mil-std. 883 (4 kv hbm) high image frequency suppre ssion due to 1 mhz if in conjunction with a saw front-end filter (up to 40 db achievable with newer saws) communication to microcontroller possibl e via a single, bi-directional data line power management (polling) is also possible by means of a separate pin via the microcontroller 1. description the ATA3742 is a multi-chip pll receiver device supplied in an so20 package. it has been specially developed for the demands of rf low-cost data transmission systems with data rates from 1 kbaud to 10 kbaud (1 kbaud to 3.2 kbaud for fsk) in manchester or bi-phase code. the receiver is well-suited to operate with atmel?s pll rf transmitter ic u2741b. its main applications in the area of wireless control are telemetering, security technology, tire-p ressure monitoring and keyless-entry sys- tems. it can be used in the frequency receiving range of f 0 = 300 mhz to 450 mhz for ask or fsk data tran smission. all the statements made in this datasheet refer both to 433.92 mhz and 315 mhz applications. uhf ask/fsk receiver ATA3742 rev. 4900a?rke?11/05
2 4900a?rke?11/05 ATA3742 figure 1-1. system block diagram figure 1-2. block diagram demod control ATA3742 1...3 u2741b antenna antenna uhf ask/fsk remote control transmitter uhf ask/fsk remote control receiver 1 li cell keys c pll xto vco lna pll vco xto encoder atarx9x power amp. fsk/ask demodulator and data filter if amp if amp 4th order lpf 3 mhz lpf 3 mhz dem_out limiter out rssi sensitivity reduction standby logic polling circuit and control logic fe clk vco xto 64 f 50 k ? v s fsk/ask cdem avcc sens agnd dgnd mixvcc lnagnd lna_in data enable test mode lfgnd lfvcc xto lf dvcc lna rssi
3 4900a?rke?11/05 ATA3742 2. pin configuration figure 2-1. pinning so20 sens fsk/ask cdem avcc agnd dgnd mixvcc lnagnd lna_in nc data enable test rssi mode dvcc xto lfgnd lf lfvcc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 table 2-1. pin description pin symbol function 1 sens sensitivity-control resistor 2 fsk/ask selecting fsk/ask low: fsk, high: ask 3 cdem lower cut-off frequency of the data filter 4 avcc analog power supply 5 agnd analog ground 6 dgnd digital ground 7 mixvcc power supply mixer 8 lnagnd high-frequency ground lna and mixer 9 lna_in rf input 10 nc not connected 11 lfvcc power supply vco 12 lf loop filter 13 lfgnd ground vco 14 xto crystal oscillator 15 dvcc digital power supply 16 mode selecting 433.92 mhz/315 mhz low: 4.90625 mhz (usa) high: 6.76438 (europe) 17 rssi output of the rssi amplifier 18 test test pin, during operation at gnd 19 enable enables the polling mode low: polling mode off (sleep mode) high: polling mode on (active mode) 20 data data output/configuration input
4 4900a?rke?11/05 ATA3742 3. rf front end the rf front end of the receiver is a heterodyne co nfiguration that converts the input signal into a 1 mhz if signal. as seen in figure 1-2 on page 2 , the front end consists of an lna (low noise amplifier), lo (local oscillator), a mixer and an rf amplifier. the lo generates the carrier frequency for the mi xer via a pll synthesize r. the xto (crystal oscillator) generates the reference frequency f xto . the vco (voltage-controlled oscillator) gen- erates the drive voltage frequency f lo for the mixer. f lo is dependent on the voltage at pin lf. f lo is divided by a factor of 64. the divided frequency is compared to f xto by the phase frequency detector. the current output of the phase frequency detector is connected to a passive loop filter and thereby generates the control voltage v lf for the vco. by means of that configuration, v lf is controlled in a way that f lo / 64 is equal to f xto . if f lo is determined, f xto can be calculated using the following formula: f xto = f lo / 64 the xto is a one-pin oscillator that operates at the series resonance of the quartz crystal. the crystal should be connected to gnd via the capacitor cl according to figure 3-1 . the value of that capacitor is recommended by the crystal su pplier. the value of cl should be optimized for the individual board layout to achieve the exact value of f xto and hereby of f lo . when designing the system in terms of receiving bandwidth, the accuracy of the crystal and the xto must be considered. figure 3-1. pll peripherals the passive loop filter connected to pin lf is designed for a loop bandwidth of b loop = 100 khz. this value for b loop exhibits the best possible noise performance of the lo. figure 3-1 shows the appropriate loop filter components to achieve the desired loop bandwidth. if the filter compo- nents are changed for any reason, please note that the maximum capacitive load at pin lf is limited. if the capacitive load is exceeded, a bit check may no longe r be possible since f lo can- not settle in time before the bit check starts to evaluate the incoming data stream. in that case, self-polling will also not work. f lo is determined by the rf input frequency f rf and the if frequency f if using the following formula: f lo = f rf ? f if dvcc xto lf lfvcc lfgnd v c c 10 r 1 c 9 s l v s r 1 = 820 ? c 9 = 4.7 nf c 10 = 1 nf
5 4900a?rke?11/05 ATA3742 to determine f lo , the construction of the if filter must be considered at this point. the nominal if frequency is f if = 1 mhz. to achieve a good accuracy of the filter's corner frequencies, the filter is tuned by the crystal frequency f xto . this means that there is a fixed relation between f if and f lo that depends on the logic level at pin mode. this is described by the following formulas: the relation is designed to achieve the nominal if frequency of f if = 1 mhz for most applica- tions. for applications where f rf = 315 mhz, mode must be set to ?0?. in the case of f rf = 433.92 mhz, mode must be set to ?1?. for other rf frequencies, f if is not equal to 1 mhz. f if is then dependent on the logical level at pin mode and on f rf . table 3-1 summarizes the dif- ferent conditions. the rf input either from an antenna or from a generator must be transformed to the rf input pin lna_in. the input impedance of that pin is provided in the electrical parameters. the para- sitic board inductances and capacitances also in fluence the input matching. the rf receiver ATA3742 exhibits its highest sensitivity at the best signal-to-noise ratio in the lna. hence, noise matching is the best choice for designing the transformation network. a good practice when designing the network is to start with power matching. from that starting point, the values of the components can be varied to some extent to achieve the best sensitivity. if a saw is implemented into the input network, a mirror frequency suppression of ? p ref = 40 db can be achieved. there are saws ava ilable that exhibit a notch at ? f = 2 mhz. these saws work best for an intermediate frequency of if = 1 mhz. the selectivity of the receiver is also improved by using a saw. in typical automotive applications, a saw is used. figure 3-2 on page 6 shows a typical input matching network for f rf = 315 mhz and f rf = 433.92 mhz using a saw. figure 3-3 on page 6 illustrates input matching to 50 ? without a saw. the input matching networks shown in figure 3-3 on page 6 are the reference networks for the parameters given in the ?electrical characteristics? on page 26 . table 3-1. calculation of lo and if frequency conditions local oscillator frequency intermediate frequency f rf = 315 mhz, mode = 0 f lo = 314 mhz f if = 1 mhz f rf = 433.92 mhz, mode = 1 f lo = 432.92 mhz f if = 1 mhz 300 mhz < f rf < 365 mhz, mode = 0 365 mhz < f rf < 450 mhz, mode = 1 mode 0 (usa) f if f lo 314 --------- - == mode 1 (europe) f if f lo 432.92 ----------------- - == f lo f rf 1 1 314 --------- - + ------------------- - = f if f lo 314 --------- - = f lo f rf 1 1 432.92 ----------------- - + --------------------------- - = f if f lo 432.92 ----------------- - =
6 4900a?rke?11/05 ATA3742 figure 3-2. input matching network with saw filter figure 3-3. input matching network without saw filter please note that for all coupling conditions (see figure 3-2 and figure 3-3 ), the bond wire induc- tivity of the lna ground is compensated. c 3 forms a series resonance circuit together with the bond wire. l = 25 nh is a feed inductor to establish a dc path. its value is not critical but must be large enough not to detune the series resonance circuit. for cost reduction, this inductor can be easily printed on the pcb. this configuration impr oves the sensitivity of the receiver by about 1 db to 2 db. in in_gnd out out_gnd case_gnd b3555 ATA3742 c 3 22p l 25n c 16 100p c 17 8.2p l 3 toko ll2012 f27nj 27n c 2 8.2p l 2 f33nj 33n 1 2 3, 4 7, 8 5 6 8 9 rf in f rf = 433.92 mhz lnagnd lna_in in in_gnd out out_gnd case_gnd b3551 ATA3742 c 3 47p l 25n c 16 100p c 17 22p l 3 toko ll2012 47nj 47n c 2 10p l 2 f82nj 82n 1 2 3, 4 7, 8 5 6 8 9 lnagnd lna_in rf in f rf = 315 mhz toko ll2012 toko ll2012 ATA3742 15p 25n 100p 3.3p f22nj 22n 8 9 rf in f rf = 433.92 mhz lnagnd lna_in ATA3742 33p 25n 100p 3.3p f39nj 39n 8 9 rf in f rf = 315 mhz lnagnd lna_in toko ll2012 toko ll2012
7 4900a?rke?11/05 ATA3742 4. analog signal processing 4.1 if amplifier the signals coming from the rf front end are filtered by the fully integrated 4th-order if filter. the if center frequency is f if = 1 mhz for applications where f rf = 315 mhz or f rf = 433.92 mhz is used. for other rf input frequencies, see table 3-1 on page 5 to determine the center frequency. the receiver ATA3742-m3 employs an if bandwidth of b if = 600 khz and can be used together with the u2741b in fsk and ask mode. 4.2 rssi amplifier the subsequent rssi amplifier enhances the output signal of the if amplifier before it is fed into the demodulator. the dynamic range of this amplifier is ? r rssi = 60 db. if the rssi amplifier is operated within its linear range, the best signal-to-noise ratio (snr) is maintained in ask mode. if the dynamic range is exceeded by the transmitter signal, the snr is defined by the ratio of the maximum rssi output voltage and the rssi output voltage due to a disturber. the dynamic range of the rssi amplifier is exceeded if the rf input signal is about 60 db higher compared to the rf input signal at full sensitivity. in fsk mode, the snr is not affected by the dynamic range of the rssi amplifier. the output voltage of the rssi amplifier is internally compared to a threshold voltage v th_red . v th_red is determined by the value of the external resistor r sense . r sense is connected between pin sens and gnd or v s . the output of the comparator is fed into the digital control logic. by this means, it is possib le to operate the receiver at a lower sensitivity. 4.3 pin rssi the output voltage of the rssi amplifier (v rssi ) is available at pin rssi. using the rssi output signal, the signal strength of different transmitters can be distinguished. the usable input-power range p ref is ? 100 dbm to ? 55 dbm. the temperature coefficient tc of v rssi is typically ? 2.2 mv/k. due to tc and gain tolerance, it is not possible to find out the abso- lute level of each transmitter, but the level differences can be used to distinguish several transmitters. as illustrated in figure 4-2 on page 8 , the rssi output voltage is not constant over the temperature range. figure 4-1 illustrates an applic ation that realizes a temperature compen- sation of v rssi .
8 4900a?rke?11/05 ATA3742 figure 4-1. temperature compensation of v rssi figure 4-2. rssi characteristic if r sense is connected to v s , the receiver operates at a lower sensitivity. the reduced sensitivity is defined by the value of r sense , the maximum sensitivity by the signal-to-noise ratio of the lna input. the reduced sensitivity is dependent on the signal strength at the output of the rssi amplifier. since different rf input networks may exhibit slig htly different values for the lna gain, the sen- sitivity values given in the electrical characte ristics refer to a specific input matching. this matching is illustrated in figure 3-3 on page 6 and exhibits the best possible sensitivity. 50k ATA3742 rssi b min = 60 v rssi i ~ ig(v lna_in ) i 47k 180k v rssi_temp_comp. 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 -110 -100 -90 -80 -70 -60 -50 p ref (dbm) v rssi (v) max min -40c 25c 105c
9 4900a?rke?11/05 ATA3742 r sense can be connected to v s or gnd via a microcontroller. the receiver can be switched from full sensitivity to reduced sensitivity or vice vers a at any time. in polling mode, the receiver will not wake up if the rf input signal does not exceed the selected sensitivity. if the receiver is already active, t he data stream at pin data will disappear when the input signal is lower than defined by the reduced sensitivity. instead of the data stream, the pattern shown in figure 4-3 is issued at pin data to indicate that the receiver is still active. figure 4-3. steady l state limited data output pattern 4.4 fsk/ask demodulator and data filter the signal coming from the rssi amplifier is converted into th e raw data signal by the ask/fsk demodulator. the operating mode of the demodulator is set via pin ask/fsk. logic ?l? sets the demodulator to fsk mode; logi c ?h? sets it into ask mode. in ask mode, an automatic threshold control circuit (atc) is employed to set the detection refer- ence voltage to a value where a good signal-to-noise ratio is achieved. this circuit also implies the effective suppression of any kind of inband noise signals or competing transmitters. if the snr exceeds 10 db, the data signal can be detected properly. the fsk demodulator is intended to be used for an fsk deviation of ? f 20 khz. lower values may be used, but the sensitivity of the receiver will be reduced. the minimum usable deviation is dependent on the selected baud rate. in fsk mode, only br_range0 and br_range1 are available. in fsk mode, the data signal can be detected if the snr exceeds 2 db. the output signal of the demodulator is filtered by t he data filter before it is fed into the digital signal processing circuit. the data filter improves the snr as its pass band can be adopted to the characteristics of the data signal. the data filter consists of a 1st-order high-pass and a 1st- order low-pass filter. the high-pass filter cut-off frequency is defined by an external capacitor connected to pin cdem. the cut-off frequency of the high-pass filter is defined by the following formula: in self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. therefore, cdem cannot be increased to very high values if self-polling is used. on the other hand, cdem must be large enough to meet the data filter requirements according to the data signal. recommended values for cdem are given in ?electrical characteristics? on page 26 . the values are slightly diffe rent for ask and fsk mode. the cut-off frequency of the low-pass filter is defined by the selected baud rate range (br_range). br_range is defined in the opmode register (refer to section ?configuration of the receiver? on page 20 ). br_range must be set in accordance to the used baud rate. the ATA3742 is designed to operate with data coding where the dc level of the data signal is 50%. this is valid for manchester and bi-phase coding. if other modulation schemes are used, the dc level should always re main within the range of v dc_min = 33% and v dc_max = 66%. the sensitivity may be reduced by up to 1.5 db in that condition. data t data_l_max t min2 f cu_df 1 2 30 k ? cdem ------------------------------------------------------------- =
10 4900a?rke?11/05 ATA3742 each br_range is also defined by a minimum and a maximum edge-to-edge time (t ee_sig ). these limits are defined in the el ectrical characteristics. they should not be exceeded to main- tain full sensitivity of the receiver. 4.5 receiving characteristics the rf receiver ATA3742 can be operated with and without a saw front-end filter. in a typical automotive application, a saw filter is used to achieve better selectivity. the selectivity with and without a saw front-end f ilter is illustrated in figure 4-4 on page 10 . this example relates to ask mode. fsk mode exhibits similar behavior. note that the mirror frequency is reduced by 40 db. the plots are printed relatively to the maximum sensitivity. if a saw filter is used, an insertion loss of about 4 db must be considered. when designing the system in te rms of receiving bandwidth, the lo deviation must be consid- ered as it also determines the if center frequen cy. the total lo deviation is calculated to be the sum of the deviation of the crystal and the xto deviation of the ATA3742. low-cost crystals are specified to be within 100 ppm. the xto deviation of the ATA3742 is an additional deviation due to the xto circuit. this deviation is specified to be 30 ppm. if a crystal of 100 ppm is used, the total deviation is 130 ppm. note that the receiving bandwidth and the if-filter band- width are equivalent in ask mode but not in fsk mode. figure 4-4. receiving freque ncy response -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 df (mhz) dp (db) without saw with saw
11 4900a?rke?11/05 ATA3742 5. polling circuit and control logic the receiver is designed to consume less than 1 ma while being sensitive to signals from a cor- responding transmitter. this is ac hieved via the polling circuit. this circuit enables the signal path periodically for a short time. during this time , the bit check logic verifies the presence of a valid transmitter signal. only if a valid signal is detected does the receiver remain active and transfer the data to the connected microcontroller. if there is no valid signal present, the receiver is in sleep mode most of the time, resulting in low current consumption. this condition is called polling mode. a connected microcontro ller is disabled during that time. all relevant parameters of the polling logic can be configured by the connected microcontroller. this flexibility enables the user to meet the specifications in terms of current consumption, sys- tem response time, data rate, etc. regarding the number of connection wires to the micr ocontroller, the receiver is very flexible. it can be either operated by a single bi-directional line to save ports to the connected microcontrol- ler, or it can be operated by up to three uni-directional ports. 5.1 basic clock cycle of the digital circuitry the complete timing of the digital circuitry and the analog filtering is derived from one clock. according to figure 5-1 on page 11 , this clock cycle t clk is derived from th e crystal oscillator (xto) in combination with a divi der. the division factor is contro lled by the logical state at pin mode. as described in section ?rf front end? on page 4 , the frequency of the crystal oscillator (f xto ) is defined by the rf input signal (f rfin ), which also defines the operating frequency of the local oscillator (f lo ). figure 5-1. generation of the basic clock cycle pin mode can now be set in accordance with the desired clock cycle t clk . t clk controls the fol- lowing application-rele vant parameters: timing of the polling circuit including bit check timing of the analog and digital signal processing timing of the register programming frequency of the reset marker if filter center frequency (f if0 ) dvcc xto mode t clk f xto 16 15 14 xto divider :14/:10 l : usa(:10) h: europe(:14)
12 4900a?rke?11/05 ATA3742 most applications are dominated by two transmission frequencies: f send = 315 mhz is mainly used in the usa, f send = 433.92 mhz in europe. in order to ease the usage of all t clk -dependent parameters, the electrical characteristics display three conditions for each parameter. application usa (f xto = 4.90625 mhz, mode = l, t clk = 2.0383 s) application europe (f xto = 6.76438 mhz, mode = h, t clk = 2.0697 s) other applications (t clk is dependent on f xto and on the logical state of pin mode. the electrical characteristic is given as a function of t clk ). the clock cycle of some function blocks depends on the selected baud rate range (br_range) which is defined in the opmode register. this clock cycle t xclk is defined by the following for- mulas for further reference: 5.2 polling mode as seen in figure 5-3 on page 15 , the receiver stays in polling mode in a continuous cycle of three different modes. in sleep mode, the signal processing circuitry is disabled for the time period t sleep while consuming low current of i s = i soff . during the start-up period, t startup , all sig- nal processing circuits are enabled and settled. in the following bit-check mode, the incoming data stream is analyzed bit by bit, looking fo r a valid transmitter signal. if no valid signal is present, the receiver is set back to sleep mode after the period t bitcheck . this period varies check by check as it is a statistical process. an average value for t bitcheck is given in the electrical char- acteristics. during t startup and t bitcheck the current consumption is i s = i son . the average current consumption in polling mode is dependent on the duty cycle of the active mode and can be cal- culated as: during t sleep and t startup , the receiver is not sensitive to a transmitter signal. to guarantee the reception of a transmitted command, the transmitt er must start the telegram with an adequate preburst. the required length of the preburst is dependent on the polling parameters t sleep , t star- tup , t bitcheck and the startup time of a connected microcontroller (t start,microcontroller ). t bitcheck thus depends on the actual bit rate and the number of bits (n bitcheck ) to be tested. the following formula indicates how to calculate the preburst length. t preburst t sleep + t startup + t bitcheck + t start_microcontroller br_range = br_range0: t xclk = 8 t clk br_range1: t xclk = 4 t clk br_range2: t xclk = 2 t clk br_range3: t xclk = 1 t clk i spoll i soff t sleep i son t startup t bitcheck + () + t sleep t startup t bitcheck ++ ------------------------------------------------------------------------------------------------------------ =
13 4900a?rke?11/05 ATA3742 5.2.1 sleep mode the length of period t sleep is defined by the 5-bit word sle ep of the opmode register, the exten- sion factor x sleep according to table 5-7 on page 22 , and the basic clock cycle t clk . it is calculated to be: t sleep = sleep x sleep 1024 t clk in us and european applications, the maximum value of t sleep is about 60 ms if x sleep is set to ?1?. the time resolution is about 2 ms in that case. the sleep time can be extended to almost half a second by setting x sleep to 8. x sleep can be set to 8 by bit x sleepstd or by bit x sleeptemp , resulting in a different mode of action as described below: x sleepstd = 1 implies the standard extension factor. the sleep time is always extended. x sleeptemp = 1 implies the temporary extension factor. the extended sleep time is used as long as every bit check is ok. if the bit check fails once, this bit is set back to ?0?, automatically result- ing in a regular sleep time. this functionality can be used to save current in the presence of a modulated disturber similar to an expected trans mitter signal. the connected microcontroller is rarely activated in that condition. if the disturbe r disappears, the receiver switches back to regu- lar polling and is again sensitive to appropriate transmitter signals. the highest register value of sleep sets the re ceiver into a permanent sleep condition (see table 5-6 on page 22 ). the receiver remains in that condition until another value for sleep is programmed into the opmode register. this func tion is desirable where several devices share a single data line. 5.2.2 bit-check mode in bit-check mode, the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. this is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a pro- grammable time window. the maximum count of these edge-to-edge tests, before the receiver switches to receiving mode, is also programmable. 5.2.3 configuring the bit check assuming a modulation scheme that contains 2 ed ges per bit, two time frame checks verify one bit. this is valid for manchester, bi-phase and most other modulation schemes. the maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable n bitcheck in the opmode register. this implies 0, 6, 12 and 18 edge-to-edge checks respectively. if n bitcheck is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. in the presence of a valid transmitter signal, th e bit check takes less time if n bitcheck is set to a lower value. in poll- ing mode, the bit check time is not dependent on n bitcheck . figure 5-1 on page 11 shows an example where 3 bits are tested successfully and the data signal is transferred to pin data. according to figure 5-2 , the time window for the bit check is defined by two separate time limits. if the edge-to-edge time t ee is in between the lower bit check limit t lim_min and the upper bit check limit t lim_max , the check will be continued. if t ee is smaller than t lim_min or t ee exceeds t lim_max , the bit check will be terminated and the receiver switc hes to sleep mode.
14 4900a?rke?11/05 ATA3742 figure 5-2. valid time window for bit check for best noise immunity it is recommended to use a low span between t lim_min and t lim_max . this is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. a ?11111...? or ?10101...? sequence in manchester or bi-phase is a good choice given this recom- mendation. a good compromise betwe en receiver sensitivity and susc eptibility to noise is a time window of 25% regarding the expected edge-to-edge time t ee . using preburst patterns that con- tain various edge-to-edge time periods, the bit check limits must be programmed according to the required span. the bit check limits are determined by means of the formula below: t lim_min = lim_min t xclk t lim_max = (lim_max ? 1) t xclk lim_min and lim_max are defined by a 5-bit word each within the limit register. using the above formulas, lim_min and lim_max can be determined according to the required t lim_min , t lim_max and t xclk . the time resolution when defining t lim_min and t lim_max is t xclk . the minimum edge-to-edge time t ee (t data_l_min , t data_h_min ) is defined according to section ?receiv- ing mode? on page 17 . due to this, the lower limit should be set to lim_min 10. the maximum value of the upper limit is lim_max = 63. dem_out t ee t lim_min t lim_max 1/f sig
15 4900a?rke?11/05 ATA3742 figure 5-3. polling mode flow chart bit check ok? sleep: 5-bit word defined by sleep0 to sleep4 in opmode register no yes sleep mode: all circuits for signal processing are disabled. only xto and polling logic are enabled. i s = i soff t sleep = sleep x sleep 1024 t clk start-up mode: the signal processing circuits are enabled. after the start-up time (t startup ) all circuits are in stable condition and ready to receive. i s = i son t startup bit-check mode: the incoming data stream is analyzed. if the timing indicates a valid transmitter signal, the receiver is set to receiving mode. otherwise it is set to sleep mode. i s = i son t bitcheck receiving mode: the receiver is turned on permanently and passes the data stream to the connected microcontroller. it can be set to sleep mode through an off command via pin data or enable i s = i son off command x sleep : extension factor defined by x sleeptemp according to table 5-7 t clk : basic clock cycle defined by f xto and pin mode t startup : is defined by the selected baud-rate range and t clk . the baud-rate range is defined by baud0 and baud1 in the opmode register. t bit-check : depends on the result of the bit check. if the bit check is ok, t bitcheck depends on the number of bits to be checked (n bitcheck ) and on the utilized data rate. if the bit check fails, the average time period for that check depends on the selected baud-rate range and on t clk . the baud-rate range is defined by baud0 and baud1 in the opmode register.
16 4900a?rke?11/05 ATA3742 figure 5-4. timing diagram for complete successful bit check figure 5-5. timing diagram during bit check figure 5-6. timing diagram for failed bit check (condition: cv_lim < lim_min) figure 5-7. timing diagram for failed bit check (condition: cv_lim lim_max) bit check enable ic data 1/2 bit startup mode number of checked bits: 3 bit check ok 1/2 bit 1/2 bit 1/2 bit 1/2 bit 1/2 bit receiving mode dem_out bit check mode bit check enable ic dem_out bit check counter 0 2345 6 245 17 81 3678911121314 10 1/2 bit 151617 18 1 2 3 4 56 lim_min = 14, lim_max = 24 7891011121314151234 1/2 bit 1/2 bit bit check ok bit check ok t startup t xclk bit check enable ic bit check counter 0 2345 6 245 1 1 3678 9 1112 10 1/2 bit startup mode 0 lim_min = 14, lim_max = 24 sleep mode bit check failed (cv_lim < lim_min) dem_out bit check mode bit check enable ic bit check counter 02345 6 245 1 7 36789 1112 10 1/2 bit startup mode 20 lim_min = 14, lim_max = 24 sleep mode bit check failed (cv_lim lim_max 13141516171819 21222324 0 1 dem_out bit check mode
17 4900a?rke?11/05 ATA3742 figure 5-5 on page 16 to figure 5-7 illustrate the bit check fo r the default bit check limits lim_min = 14 and lim_max = 24. when the ic is enabled, the signal processing circuits are enabled during t startup . the output of the ask/fsk demodulator (dem_out) is undefined during that period. when the bit check bec omes active, the bit check count er is clocked with the cycle t xclk . figure 5-5 on page 16 shows how the bit check proceeds if the bit check counter value cv_lim is within the limits defined by lim_min and lim_max at the occurrence of a signal edge. in fig- ure 5-6 on page 16 , the bit check fails as the value cv_lim is lower than the limit lim_min. the bit check also fails if cv_lim reac hes lim_max. this is illustrated in figure 5-7 . 5.2.4 duration of the bit check if no transmitter signal is present during the bit check, the output of the ask/fsk demodulator delivers random signals. the bit check is a statistical process and t bitcheck varies for each check. therefore, an average value for t bitcheck is given in the electrical characteristics. t bitcheck depends on the selected baud rate range and on t clk . a higher baud rate range causes a lower value for t bitcheck resulting in a lower curren t consumption in polling mode. in the presence of a valid transmitter signal, t bitcheck is dependent on the frequency of that sig- nal, f sig , and on the count of the checked bits, n bitcheck . a higher value for n bitcheck thereby results in a longer period for t bitcheck requiring a higher value for the transmitter preburst t preburst . 5.3 receiving mode if the bit check is successful for all bits specified by n bitcheck , the receiver switches to receiving mode. as shown in figure 5-4 on page 16 , the internal data signal is switched to pin data in that case. a connected microcontroller can be woken up by the negative edge at pin data. the receiver stays in that condition until it is switched back to polling mode explicitly. 5.3.1 digital signal processing the data from the ask/fsk demodulator (dem_out) is digitally processed in different ways and as a result converted into the output signal data . this processing depends on the selected baud rate range (br_range). figure 5-8 on page 18 illustrates how dem_out is synchronized by the extended clock cycle t xclk . this clock is also used for the bit check counter. data can change its state only after t xclk elapses. the edge-to-edge time period t ee of the data signal as a result is always an integral multiple of t xclk . the minimum time period between two edges of the data signal is limited to t ee t data_min . this implies an efficient suppression of spikes at the data output. at the same time, it limits the max- imum frequency of edges at data. this eases the interrupt handling of a connected microcontroller. t data_min is to some extent affected by the preceding edge-to-edge time interval t ee as illustrated in figure 5-9 . if t ee is in between the specified bi t check limits, the following level is frozen for the time period t data_min = tmin1, in case of t ee being outside that bit check limits t data_min = tmin2 is the relevant stable time period. the maximum time period for data to be low is limited to t data_l_max . this function ensures a finite response time during programming or switching off the receiver via pin data. t data_l_max is thereby longer than the maximum time period indicated by the transmitter data stream. figure 5-10 gives an example where dem_out remains low after the receiver is in receiving mode.
18 4900a?rke?11/05 ATA3742 figure 5-8. synchronization of the demodulator output figure 5-9. debouncing of the demodulator output figure 5-10. steady l state limited data output pattern after transmission after the end of data transmission, the receiver remains active and random noise pulses appear at pin data. the edge-to-edge time period t ee of the majority of these noise pulses is equal to or slightly higher than t data_min . clock bit check counter data t xclk dem_out t ee data tmin1 cv_lim < lim_min or cv_lim lim_max lim_min cv_lim < lim_max dem_out t ee tmin2 t ee bit check enable ic data startup mode receiving mode tmin2 bit check mode t data_l_max dem_out
19 4900a?rke?11/05 ATA3742 5.3.2 switching the receiver back to sleep mode the receiver can be set back to polling mode via pin data or via pin enable. when using pin data, this pin must be pulled to low for the period t 1 by the connected micro- controller. figure 5-11 illustrates the timing of the off command (see also figure 5-15 on page 24 ). the minimum value of t 1 depends on br_range. the maximum value for t 1 is not limited but it is recommended not to exceed the specified value to prevent erasing the reset marker. this item is explained in more detail in section ?configuration of the receiver? on page 20 . set- ting the receiver to sleep mode via data is achieved by programming bit 1 of the opmode register to be ?1?. only one sync pulse (t 3 ) is issued. the duration of the off command is determined by the sum of t 1 , t 2 and t 10 . after the off com- mand, the sleep time t sleep elapses. note that the capacitive load at pin data is limited. the resulting time constant together with an optional external pull-up resistor may not be exceeded to ensure proper operation. if the receiver is set to polling mode via pin enable, an ?l? pulse (t doze ) must be issued at that pin. figure 5-12 on page 20 illustrates the timing of that comm and. after the positive edge of this pulse, the sleep time t sleep elapses. the receiver remains in sleep mode as long as enable is held to ?l?. if the receiver is polled exclusively by a microcontroller, t sleep can be programmed to ?0? to enable an instantaneous response time. th is command is a faster option than via pin data, at the cost of an additional connection to the microcontroller. figure 5-11. timing diagram of the off command via pin data out1 (microcontroller) data (ATA3742) serial bi-directional data line x bit 1 ("1") x t 1 t 3 (startbit) startup mode off command t sleep receiving mode t 2 t 4 t 5 t 10 t 7
20 4900a?rke?11/05 ATA3742 figure 5-12. timing diagram of the off command via pin enable 5.4 configuration of the receiver the ATA3742 receiver is configured via two 12 -bit ram registers called opmode and limit. the registers can be programmed by means of the bi-directional data port. if the register con- tents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (rm). the receiver must be reprogrammed in that case. after a power-on reset (por), the registers are set to default mode. if the receiver is operated in default mode, there is no need to program the registers. table 5-2 on page 21 shows the structure of the registers. refering to table 5-1 , bit 1 defines if the receiver is set back to polling mode via the o ff command (see section ?receiving mode? on page 17 ), or if it is programmed. bit 2 represents the register address. it selects the appropri- ate register to be programmed. table 5-3 on page 21 and the following illustrate the effect of the individual configuration words. the default configuration is highlighted for each word. br_range sets the appropriate baud rate range. at the same time it defines xlim. xlim is used to define the bit check limits t lim_min and t lim_max as shown in table 5-3 on page 21 . enable data (ATA3742) serial bi-directional data line x x t off receiving mode startup mode t sleep t doze table 5-1. effect of bit 1 and bit 2 in programming the registers bit 1 bit 2 action 1 x the receiver is set back to polling mode (off command) 0 1 the opmode register is programmed 0 0 the limit register is programmed
21 4900a?rke?11/05 ATA3742 table 5-2. effect of the configuration words within the registers bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 off command 1 opmode register 0 1 br_range n bitcheck v pout sleep x sleep 0 1 baud1 baud0 bitchk1 bitchk0 pout sleep4 sleep3 sleep2 sleep1 sleep0 x sleep std x sleep temp (default)00100010110 0 limit register 0 0 lim_min lim_max 0 0 lim_min5 lim_min4 lim_min3 lim_min2 lim_min1 lim_min0 lim_max5 lim_max4 lim_max3 lim_max2 lim_max1 lim_max0 (default)00111001100 0 table 5-3. effect of the configuration word br_range br_range baud rate range/extension factor for bit check limits (xlim) baud1 baud0 00 br_range0 (application usa/europe: br_range0 = 1.0 kbaud to 1.8 kbaud) (default) xlim = 8 (default) 01 br_range1 (application usa/europe: br _range1 = 1.8 kbaud to 3.2 kbaud) xlim = 4 10 br_range2 (application usa/europe: br _range2 = 3.2 kbaud to 5.6 kbaud) xlim = 2 11 br_range3 (application usa/europe: br_range3 = 5.6 kbaud to 10 kbaud) xlim = 1 table 5-4. effect of the configuration word n bitcheck n bitcheck number of bits to be checked bitchk1 bitchk0 00 0 01 3 1 0 6 (default) 11 9 table 5-5. effect of the configuration bit reserved reserved bit no function (r eserved for future use) 0 (default) 1-
22 4900a?rke?11/05 ATA3742 table 5-6. effect of the configuration word sleep sleep start value for sleep counter (t sleep = sleep x sleep 1024 t clk ) sleep4 sleep3 slee p2 sleep1 sleep0 000000 (receiver is continuously polling until a valid signal occurs) 000011 (t sleep 2 ms for x sleep = 1 in us/european applications) 00010 2 00011 3 . . . . . . . . . . . . . . . . . . 0101111 (usa: t sleep = 22.96 ms, europe: t sleep = 23.31 ms) (default) . . . . . . . . . . . . . . . . . . 11101 29 11110 30 11111 31 (permanent sleep mode) table 5-7. effect of the configuration word x sleep x sleep extension factor for sleep time (t sleep = sleep x sleep 1024 t clk ) x sleepstd x sleeptemp 0 0 1 (default) 01 8 (x sleep is reset to 1 if bit check fails once) 10 8 (x sleep is set permanently) 11 8 (x sleep is set permanently) table 5-8. effect of the configuration word lim_min lim_min lower limit value for bit check lim_min < 10 is not applicable (t lim_min = lim_min xlim t clk ) 001010 10 001011 11 001100 12 001101 13 001110 14 (default) (usa: t lim_min = 228 s, europe: t lim_min = 232 s) . . . . . . . . . . . . . . . . . . . . . 111101 61 111110 62 111111 63
23 4900a?rke?11/05 ATA3742 5.4.1 conservation of the register information the ATA3742 has an integrated power-on reset (por) and brown-out detection circuitry to pro- vide a mechanism to preserve the ram register information. according to figure 5-13 , a power-on reset is generated if the supply voltage v s drops below the threshold voltage v threset . the default parameters are programmed into the configuration regis- ters in that condition. once v s exceeds v threset , the por is canceled after the minimum reset period t rst . a por is also generated when the supply voltage of the receiver is turned on. to indicate that condition, the receiver displays a reset marker (rm) at pin data after a reset. the rm is represented by the fixed frequency f rm at a 50% duty cycle. rm can be canceled via an ?l? pulse t 1 at pin data. the rm implies the following characteristics: f rm is lower than the lowest feasible frequency of a data signal. this means, rm cannot be misinterpreted by the connected microcontroller. if the receiver is set back to polling mode vi a pin data, rm cannot be cancelled by accident if t 1 is applied according to the proposal in the section ?programming the configuration register? on page 24 . by means of that mechanism, the receiver cannot lose its register information without communi- cating that condition via the reset marker rm. table 5-9. effect of the configuration word lim_max lim_max upper limit value for bit check lim_max < 12 is not applicable (t lim_max = (lim_max ? 1) xlim t clk ) 001100 12 001101 13 001110 14 . . . . . . . . . . . . . . . . . . . . . 011000 24 (default) (usa: t lim_max = 375 s, europe: t lim_max = 381 s) . . . . . . . . . . . . . . . . . . . . . 111101 61 111110 62 111111 63
24 4900a?rke?11/05 ATA3742 figure 5-13. generation of the power-on reset figure 5-14. timing of the register programming 5.4.2 programming the c onfiguration register the configuration registers are programmed serially via the bi-directional data line according to figure 5-14 and figure 5-15 . figure 5-15. one-wire connection to a microcontroller v s por data (ATA3742) x 1/f rm t rst v threset out1 (microcontroller) data (ATA3742) serial bi-directional data line x bit 1 ("0") bit 2 ("1") bit 13 ("0") bit 14 ("1") x t 8 t sleep programming frame (startbit) (register- select) (poll8) (poll8r) receiving mode startup mode t 9 t 7 t 6 t 5 t 4 t 3 t 2 t 1 internal pull-up resistor bi-directional data line data i/o ATA3742 microcontroller data (ATA3742) out 1 (microcontroller)
25 4900a?rke?11/05 ATA3742 to start programming, the serial data line data is pulled to ?l? for the time period t 1 by the microcontroller. when data has been released, th e receiver becomes the master device. when the programming delay period t 2 has elapsed, it emits 14 subsequent synchronization pulses with the pulse length t 3 . after each of these pulses, a programming window occurs. the delay until the program window starts is determined by t 4 , the duration is defined by t 5 . within the pro- gramming window, the individual bits are set. if the microcontroller pulls down pin data for the time period t 7 during t 5 , the bit is set to ?0?. if no programming pulse t 7 is issued, this bit is set to ?1?. all 14 bits are subsequently programmed in this way. the time frame to program a bit is defined by t 6 . bit 14 is followed by the equivalent time window t 9 . during this window, the equivalent acknowl- edge pulse t 8 (e_ack) occurs if the just-programmed mode word is equivalent to the mode word that was already stored in that register. e_ack should be used to verify that the mode word was correctly transferred to the register. the register must be programmed twice in that case. programming of a register is possible both du ring sleep and active mode of the receiver. during programming, the lna, lo, low-pass filter, if amplifier and the fsk/ask manchester demodulator are disabled. the programming start pulse t 1 initiates the programming of the configuration registers. if bit 1 is set to ?1?, it represen ts the off command to set the receiver back to po lling mode at the same time. for the length of the programming start pulse t 1 , the following convention should be considered: t 1 (min) < t 1 < 1535 t clk : [t 1 (min) is the minimum specified va lue for the relevant br_range] programming (or the off command) is initiated if the receiver is not in reset mode. if the receiver is in reset mode, programming (or the off command) is not initiated, and the reset marker (rm) is still present at pin data. this period is generally used to switch the receiv er to polling mode. in a reset condition, rm is not canceled by accident. t 1 > 5632 t clk programming (or the off command ) is initiated in any case. rm is canceled if present. this period is used if the connected microcontr oller detected rm. if a configuration register is programmed, this time period for t 1 can generally be used. note that the capacitive load at pin data is limited. the resulting ti me constant t together with an optional external pull-up resistor may not be exceeded to ensure proper operation.
26 4900a?rke?11/05 ATA3742 6. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol min. max. unit power dissipation p tot 450 mw junction temperature t j 150 c storage temperature t stg ?55 +125 c ambient temperature t amb ?40 +105 c maximum input level, input matched to 50 ? p in_max 10 dbm 7. thermal resistance parameters symbol value unit junction ambient r thja 100 k/w 8. electrical characteristics all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (v s = 5v, t amb = 25c) parameter test condition symbol 6.76438 mhz oscillator (mode 1) 4.90625 mhz oscillator (mode 0) variable oscillator unit min. typ. max. min. typ. max. min. typ. max. basic clock cycle of the digital circuitry basic clock cycle mode = 0 (usa) mode = 1 (europe) t clk 2.0697 2.0383 1 / (f xto / 10) 1 / (f xto / 14) s s extended basic clock cycle br_range0 br_range1 br_range2 br_range3 t xclk 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 8 t clk 4 t clk 2 t clk 1 t clk s s s s polling mode sleep time sleep and x sleep are defined in the opmode register t sleep sleep x sleep 1024 2.0697 sleep x sleep 1024 2.0383 sleep x sleep 1024 t clk ms start-up time br_range0 br_range1 br_range2 br_range3 t startup 1855 1061 1061 663 1827 1045 1045 653 896.5 512.5 512.5 320.5 t clk s s s s time for bit check average bit-check time while polling br_range0 br_range1 br_range2 br_range3 t bitcheck 0.45 0.24 0.14 0.14 0.47 0.26 0.16 0.15 ms ms ms ms bit-check time for a valid input signal f sig n bitcheck = 0 n bitcheck = 3 n bitcheck = 6 n bitcheck = 9 t bitcheck 3 / f sig 6 / f sig 9 / f sig 3.5 / f sig 6.5 / f sig 9.5 / f sig 3 / f sig 6 / f sig 9 / f sig 3.5 / f sig 6.5 / f sig 9.5 / f sig t xclk 3 / f sig 6 / f sig 9 / f sig t xclk 3.5 / f sig 6.5 / f sig 9.5 / f sig ms ms ms ms
27 4900a?rke?11/05 ATA3742 receiving mode intermediate frequency mode=0 (usa) mode=1 (europe) f if 1.0 1.0 f xto 64 / 314 f xto 64 / 432.92 mhz mhz baud-rate range br_range0 br_range1 br_range2 br_range3 br_range 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 br_range0 2 s / t clk br_range1 2 s / t clk br_range2 2 s / t clk br_range3 2 s / t clk kbaud kbaud kbaud kbaud minimum time period between edges at pin data ( figure 5-9 on page 18 ) br_range0 br_range1 br_range2 br_range3 t data_min tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 149 182 75 91 37.3 45.5 18.6 22.8 147 179 73 90 36.7 44.8 18.3 22.4 9 t xclk 11 t xclk 9 t xclk 11 t xclk 9 t xclk 11 t xclk 9 t xclk 11 t xclk s s s s s s s s maximum low period at data ( figure 5-10 on page 18 ) br_range0 br_range1 br_range2 br_range3 t data_l_max 2169 1085 542 271 2136 1068 534 267 131 t xclk 131 t xclk 131 t xclk 131 t xclk s s s s off command at pin enable ( figure 5-12 on page 20 ) t doze 3.1 3.05 1.5 t clk s configuration of the receiver frequency of the reset marker ( figure 5-13 on page 24 ) f rm 117.9 119.8 hz programming start pulse ( figure 5-11 on page 19 , figure 5-14 on page 24 ) br_range0 br_range1 br_range2 br_range3 after por t 1 2188 1104 561 290 11656 3176 3176 3176 3176 2155 1087 553 286 11479 3128 3128 3128 3128 1057 t clk 533 t clk 271 t clk 140 t clk 5632 t clk 1535 t clk 1535 t clk 1535 t clk 1535 t clk s programming delay period ( figure 5-11 on page 19 , figure 5-14 on page 24 ) t 2 795 798 783 786 384.5 t clk 385.5 t clk s 8. electrical characteristics (continued) all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (v s = 5v, t amb = 25c) parameter test condition symbol 6.76438 mhz oscillator (mode 1) 4.90625 mhz oscillator (mode 0) variable oscillator unit min. typ. max. min. typ. max. min. typ. max. 1 4096 t clk ----------------------------------
28 4900a?rke?11/05 ATA3742 synchroni- zation pulse ( figure 5-11 on page 19 , figure 5-14 on page 24 ) t 3 265 261 128 t clk s delay until the program window starts ( figure 5-11 on page 19 , figure 5-14 on page 24 ) t 4 131 129 63.5 t clk s programming window ( figure 5-11 on page 19 , figure 5-14 on page 24 ) t 5 530 522 256 t clk s time frame of a bit ( figure 5-14 on page 24 ) t 6 1060 1044 512 t clk s programming pulse ( figure 5-11 on page 19 , figure 5- 14 on page 24 ) t 7 133 529 131 521 64 t clk 256 t clk s equivalent acknowledge pulse: e_ack ( figure 5-14 on page 24 ) t 8 265 261 128 t clk s equivalent time window ( figure 5-14 on page 24 ) t 9 534 526 258 t clk s off-bit programming window ( figure 5-11 on page 19 ) t 10 930 916 449.5 t clk s 8. electrical characteristics (continued) all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (v s = 5v, t amb = 25c) parameter test condition symbol 6.76438 mhz oscillator (mode 1) 4.90625 mhz oscillator (mode 0) variable oscillator unit min. typ. max. min. typ. max. min. typ. max.
29 4900a?rke?11/05 ATA3742 9. electrical characteristics all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (v s = 5v, t amb = 25c) parameters test conditions symbol min. typ. max. unit current consumption sleep mode (xto and polling logic active) is off 190 350 a ic active (start up, bit check, receiving mode) pin data = h is on 7.0 8.6 ma lna mixer third-order intercept point lna/mixer/if amplifier input matched according to figure 3-3 on page 6 iip3 ?28 dbm lo spurious emission at rf in input matched according to figure 3-3 on page 6 , required according to i-ets 300220 is lorf ?73 ?57 dbm noise figure lna and mixer (dsb) input matching according to figure 3-3 on page 6 nf 7 db lna_in input impedance at 433.92 mhz at 315 mhz zi lna_in 1.0 || 1.56 1.3 || 1.0 k ? || pf k ? || pf 1 db compression point (lna, mixer, if amplifier) input matched according to figure 3-3 on page 6 , referred to rf in ip 1db ?40 dbm maximum input level input matched according to figure 3-3 on page 6 , ber 10 -3 , ask mode p in_max ?28 ?20 dbm dbm local oscillator operating frequency range vco f vco 299 449 mhz phase noise vco/lo f osc = 432.92 mhz at 1 mhz at 10 mhz l (fm) ?93 ?113 ?90 ?110 dbc/hz dbc/hz spurious of the vco at f xto ?55 ?47 dbc vco gain k vco 190 mhz/v loop bandwidth of the pll for best lo noise (design parameter) r 1 = 820 ? c 9 = 4.7 nf c 10 = 1 nf b loop 100 khz capacitive load at pin lf the capacitive load at pin lf is limited if bit check is us ed. the limitation therefore also applies to self-polling. c lf_tot 10 nf xto operating frequency xto crystal frequency, appropriate load capacitance must be connected to xtal 6.764375 mhz 4.90625 mhz f xto 6.764375 ?30 ppm 4.90625 ?30 ppm 6.764375 4.90625 6.764375 +30 ppm 4.90625 +30 ppm mhz mhz series resonance resistor of the crystal f xto = 6.764 mhz 4.906 mhz r s 150 220 ? ?
30 4900a?rke?11/05 ATA3742 static capacitance of the crystal c xto 6.5 pf analog signal processing input sensitivity ask input matched according to figure 3-3 on page 6 ask (level of carrier) ber 10 -3 , f if = 1 mhz f in = 433.92 mhz/315 mhz t = 25c, v s = 5v p ref_ask input sensitivity ask br_range0 ?108 ?110 ?112 dbm br_range1 ?106.5 ?108.5 ?110.5 dbm br_range2 ?106 ?108 ?110 dbm br_range3 ?104 ?106 ?108 dbm sensitivity variation ask for the full operating range compared to t amb = 25c, v s = 5v f in = 433.92 mhz/315 mhz f if = 1 mhz p ask = p ref_ask + ? p ref ? p ref +2.5 ?1.5 db sensitivity variation ask for full operating range including if filter compared to t amb = 25c, v s = 5v f in = 433.92 mhz/315 mhz f if = 0.79 mhz to 1.21 mhz f if = 0.73 mhz to 1.27 mhz p ask = p ref_ask + ? p ref ? p ref +5.5 +7.5 ?1.5 ?1.5 db db input sensitivity fsk input matched according to figure 3-3 on page 6 , ber 10 -3 , f if = 1 mhz f in = 433.92 mhz/315 mhz t = 25c, v s = 5v p ref_fsk input sensitivity fsk br_range0 df 20 khz df 30 khz ?95.5 ?96.5 ?97.5 ?98.5 ?99.5 ?100.5 dbm dbm br_range1 df 20 khz df 30 khz ?94.5 ?95.5 ?96.5 ?97.5 ?98.5 ?99.5 dbm dbm sensitivity variation fsk for the full operating range compared to t amb = 25c, v s = 5v f in = 433.92 mhz/315 mhz f if = 1 mhz p fsk = p ref_fsk + ? p ref ? p ref +2.5 ?1.5 db sensitivity variation fsk for full operating range including if filter compared to t amb = 25c, v s = 5v f in = 433.92 mhz/315 mhz f if = 0.86 mhz to 1.14 mhz f if = 0.82 mhz to 1.18 mhz p fsk = p ref_fsk + ? p ref ? p ref +5.5 +7.5 ?1.5 ?1.5 db db fsk frequency deviation the sensitivity of the receiver is higher for higher values of ? f fsk br_range0 br_range1 br_range2 and br_range3 are not suitable for fsk operation ? f fsk 20 20 30 30 50 50 khz khz snr to suppress inband noise signals ask mode fsk mode snr ask snr fsk 10 2 12 3 db db dynamic range rssi amplifier ? r rssi 60 db 9. electrical characteristics (continued) all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (v s = 5v, t amb = 25c) parameters test conditions symbol min. typ. max. unit
31 4900a?rke?11/05 ATA3742 lower cut-off frequency of the data filter f cu_df 0.11 0.16 0.20 khz recommended cdem for best performance ask mode br_range0 (default) br_range1 br_range2 br_range3 cdem 39 22 12 8.2 nf nf nf nf recommended cdem for best performance fsk mode br_range0 (default) br_range1 br_range2 and br_range3 are not suitable for fsk operation cdem 27 15 nf nf maximum edge-to-edge time period of the input data signal fo r full sensitivity br_range0 (default) br_range1 br_range2 br_range3 t ee_sig 1000 560 320 180 s s s s upper cut-off frequency data filter upper cut-off frequency programmable in 4 ranges via a serial mode word br_range0 (default) br_range1 br_range2 br_range3 f u 2.5 4.3 7.6 13.6 3.1 5.4 9.5 17.0 3.7 6.5 11.4 20.4 khz khz khz khz minimum edge-to-edge time period of the input data signal fo r full sensitivity br_range0 (default) br_range1 br_range2 br_range3 t ee_sig 270 156 89 50 s s s s reduced sensitivity r sense connected from pin sens to v s , input matched according to figure 3-3 on page 6 p ref_red dbm (peak level) reduced sensitivity (v s = 5v, t amb = 25c) r sense = 56 k ? , f in = 433.92 mhz, ?67 ?72 ?77 dbm r sense = 100 k ? , f in = 433.92 mhz ?76 ?81 ?86 dbm r sense = 56 k ? , f in = 315 mhz ?68 ?73 ?78 dbm r sense = 100 k ? , f in = 315 mhz ?77 ?82 ?87 dbm reduced sensitivity variation over full operating range r sense = 56 k ? r sense = 100 k ? p red = p ref_red + ? p red ? p red 5 6 0 0 0 0 db db reduced sensitivity variation for different values of r sense values relative to r sense = 56 k ? r sense = 56 k ? r sense = 68 k ? r sense = 82 k ? r sense = 100 k ? r sense = 120 k ? r sense = 150 k ? p red = p ref_red + ? p red ? p red 0 ?3.5 ?6.0 ?9.0 ?11.0 ?13.5 db db db db db db 9. electrical characteristics (continued) all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (v s = 5v, t amb = 25c) parameters test conditions symbol min. typ. max. unit f cu_df 1 2 30 k ? cdem ------------------------------------------------------------- =
32 4900a?rke?11/05 ATA3742 threshold voltage for reset v threset 1.95 2.8 3.75 v digital ports data output - saturation voltage low - internal pull-up resistor - maximum time constant - maximum capacitive load i ol = 1 ma = c l (r pup //r ext ) without external pull-up resistor r ext = 5 k ? v oi r pup c l c l 39 0.08 50 0.3 61 2.5 41 540 v k ? s pf pf fsk/ask input - low-level input voltage - high-level input voltage fsk selected ask selected v il v ih 0.8 v s 0.2 v s v v enable input - low-level input voltage - high-level input voltage idle mode active mode v il v ih 0.8 v s 0.2 v s v v mode input - low-level input voltage - high-level input voltage division factor = 10 division factor = 14 v il v ih 0.8 v s 0.2 v s v v test input - low-level input voltage test input must always be set to low v il 0.2 v s v 9. electrical characteristics (continued) all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (v s = 5v, t amb = 25c) parameters test conditions symbol min. typ. max. unit
33 4900a?rke?11/05 ATA3742 11. package information 10. ordering information extended type number package remarks ATA3742p3-tgsy so20 tube, pb-free ATA3742p3-tgqy so20 taped and reeled, pb-free technical drawings according to din specifications package so20 dimensions in mm 9.15 8.65 11.43 12.95 12.70 2.35 0.25 0.10 0.4 1.27 7.5 7.3 0.25 10.50 10.20 20 11 110
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